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p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family with extended memory; 64 kb/96 kb otp with 2 kb/3 kb ram rev. 03 13 november 2003 product data 1. general description the p87c51mx2 represents the ?rst microcontroller based on philips semiconductors new 51mx core. the p87c51mc2 features 96 kbytes of otp program memory and 3 kbytes of data sram, while the p87c51mb2 has 64 kbytes of otp and 2 kbytes of ram. in addition, both devices are equipped with a programmable counter array (pca), a watchdog timer that can be con?gured to different time ranges through sfr bits, as well as two enhanced uarts and serial peripheral interface (spi). philips semiconductors 51mx (memory extension) core is an accelerated 80c51 architecture that executes instructions at twice the rate of standard 80c51 devices. the linear address range of the 51mx has been expanded to support up to 8 mbytes of program memory and 8 mbytes of data memory. it retains full program code compatibility to enable design engineers to re-use 80c51 development tools, eliminating the need to move to a new, unfamiliar architecture. the 51mx core also retains 80c51 bus compatibility to allow for the continued use of 80c51-interfaced peripherals and application speci?c integrated circuits (asics). the p87c51mx2 provides greater functionality, increased performance and overall lower system cost. by offering an embedded memory solution combined with the enhancements to manage the memory extension, the p87c51mx2 eliminates the need for software work-around. the increased program memory enables design engineers to develop more complex programs in a high-level language like c, for example, without struggling to contain the program within the traditional 64 kbytes of program memory. these enhancements also greatly improve c language ef?ciency for code size below 64 kbytes. the 51mx core is described in more detail in the 51mx architecture reference . 2. features 2.1 key features n extended features of the 51mx core: u 23-bit program memory space and 23-bit data memory space u linear program and data address range expanded to support up to 8 mbytes each u program counter expanded to 23 bits u stack pointer extended to 16 bits enabling stack space beyond the 80c51 limitation
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 2 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. u new 23-bit extended data pointer and two 24-bit universal pointers greatly improve c compiler code ef?ciency in using pointers to access variables in different spaces n 100% binary compatibility with the classic 80c51 so that existing code is completely reusable n up to 24 mhz cpu clock with 6 clock cycles per machine cycle n 96 kbytes (mc2) or 64 kbytes (mb2) of on-chip otp n 3 kbytes (mc2) or 2 kbytes (mb2) of on-chip ram n programmable counter array (pca) n two full-duplex enhanced uarts and serial peripheral interface (spi) communication modules 2.2 key bene?ts n increases program/data address range to 8 mbytes each n enhances performance and ef?ciency for c programs n fully 80c51-compatible microcontroller n provides seamless and compelling upgrade path from classic 80c51 n preserves 80c51 code base, investment/knowledge, and peripherals & asics n supported by wide range of 80c51 development systems and programming tools vendors n the p87c51mx2 makes it possible to develop applications at lower cost and with a reduced time-to-market 2.3 complete features n fully static n up to 24 mhz cpu clock with 6 clock cycles per machine cycle n 96 kbytes or 64 kbytes of on-chip otp n 3 kbytes or 2 kbytes of on-chip ram n 23-bit program memory space and 23-bit data memory space n four-level interrupt priority n 34 i/o lines (5 ports) n three timers: timer0, timer1 and timer2 n two full-duplex enhanced uarts with baud rate generator n framing error detection n automatic address recognition n supports industry-standard serial peripheral interface (spi) with a baud rate up to 6 mbits/s n power control modes n clock can be stopped and resumed n idle mode n power down mode with advanced clock control n second dptr register n asynchronous port reset n programmable counter array (pca) (compatible with 8xc51rx+) with ?ve capture/compare modules
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 3 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. n low emi (inhibit ale) n watchdog timer with programmable prescaler for different time ranges (compatible with 8xc66x with added prescaler) 3. differences between p87c51mx2/02 part and previous revisions of p87c51mx2 the p87c51mx2/02 offers several advantages over the previous generation of p87c51mx2 parts. right now, spi module is available, two more general purpose digital pins on p4 are present and additional power control features are implemented (advanced peripheral clock control). new memory interface mode and code size optimization options are available with the use of mxcon register. no changes are necessary when porting and loading code written for existing p87c51mx2 to the new p87c51mx2/02. 4. ordering information table 1: ordering information type number memory temp range ( c) v dd voltage range frequency package otp ram v dd = 2.7 to 5.5 v v dd = 4.5 to 5.5 v name description version P87C51MB2BA/02 64 kb 2048 b 0 to +70 2.7 to 5.5 v 0 to 12 mhz 0 to 24 mhz plcc44 plastic leaded chip carrier; 44 leads sot187-2 p87c51mc2ba/02 96 kb 3072 b 0 to +70 2.7 to 5.5 v 0 to 12 mhz 0 to 24 mhz plcc44 plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 4 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 5. block diagram fig 1. block diagram. 002aaa148 high performance 80c51 cpu (51 mx core) 96kb/64kb code eprom 3kb/2kb data ram port 4 port 3 port 2 port 1 port 0 configurable i/os oscillator crystal or resonator uart 0 baud rate generator uart 1 spi timer 0 timer 1 timer 2 pca (programmable counter array) watchdog timer internal bus
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 5 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 6. functional diagram fig 2. functional diagram. p87c51mx2 port1 port2 address bus 8-15 address bus 16-22 t2 t2ex eci cex0 cex1 cex2 cex3 cex4 mosi spiclk xtal2 xtal1 v dd v ss address bus 0-7 data bus port0 port 4 port 3 rxd0 txd0 rxd1 txd1 int0 int1 t0 rst ea/v pp psen ale/prog t1 wr rd miso ss 002aaa147
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 6 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 7. pinning information 7.1 pinning fig 3. pinning. p87c51mb2/ p87c51mc2 002aaa165 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 1 44 43 42 41 40 p1.4/cex1/mosi p1.3/cex0 p1.2/eci p1.1/t2ex p1.0/t2 (nc/v ss ) v dd p0.0/ad0 p0.1/ad1 p0.2/ad2 p0.3/ad3 p3.6/wr p3.7/rd xtal2 xtal1 v ss (nc/v dd ) p2.0/a8/a16 p2.1/a9/a17 p2.2/a10/a18 p2.3/a11/a19 p2.4/a12/a20 p1.5/cex2/spiclk p1.6/cex3 p1.7/cex4 rst p3.0/rxd0 p4.0/rxd1/mis0 p3.1/txd0 p3.2/int0 p3.3/int1 p3.4/t0 p3.5/t1 p0.4/ad4 p0.5/ad5 p0.6/ad6 p0.7/ad7 ea/v pp p4.1/txd1/ss ale psen p2.7/a15 p2.6/a14/a22 p2.5/a13/a21
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 7 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 7.2 pin description table 2: pin description symbol pin type description p0.0 - p0.7 43 - 36 i/o port 0: port 0 is an open drain, bidirectional i/o port. port 0 pins that have 1s written to them ?oat and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. p1.0 - p1.7 2 - 9 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups on all pins. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. 2 i/o ? p1.0, t2 C timer/counter 2 external count input/clock out 3i ? p1.1, t2ex C timer/counter 2 reload/capture/direction control 4i ? p1.2, eci C external clock input to the pca 5 i/o ? p1.3, cex0 C capture/compare external i/o for pca module 0 6 i/o ? p1.4, cex1 C capture/compare external i/o for pca module 1 (with pull-up on pin) i/o ? mosi C spi master out/slave in (selected when spen (spctl.6) is 1, in which case the pull-up for this pin is disabled) 7 i/o ? p1.5, cex2 C capture/compare external i/o for pca module 2 (with pull-up on pin) i/o ? spiclk C spi clock (selected when spen (spctl.6) is 1, in which case the pull-up for this pin is disabled) 8 i/o ? p1.6, cex3 C capture/compare external i/o for pca module 3 9 i/o ? p1.7, cex4 C capture/compare external i/o for pca module
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 8 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. p2.0 - p2.7 24 - 31 i/o port 2: port 2 is a 8-bit bidirectional i/o port with internal pull-ups on all pins. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see section 10 static characteristics , i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @ dptr) or 23-bit addresses (movx @eptr, emov). in this application, it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (mov @ ri), port 2 emits the contents of the p2 special function register. note that when 23-bit address is used, address bits a16-a22 will be outputted to p2.0-p2.6 when ale is high, and address bits a8-a14 are outputted to p2.0-p2.6 when ale is low. address bit a15 is outputted on p2.7 regardless of ale. p3.0 - p3.7 11,13 -19 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally pulled low will source current because of the internal pull-ups. 11 i ? p3.0, rxd0 C serial input port 0 13 o ? p3.1, txd0 C serial output port 0 14 i ? p3.2, int0 C external interrupt 0 15 i ? p3.3, int1 C external interrupt 1 16 i ? p3.4, t0 C timer0 external input 17 i ? p3.5, t1 C timer1 external input 18 o ? p3.6, wr C external data memory write strobe 19 o ? p3.7, rd C external data memory read strobe p4.0 - p4.1 12,34 i/o port 4: port 4 is an 2-bit bidirectional i/o port with internal pull-ups on all pins. port 4 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 4 pins that are externally pulled low will source current because of the internal pull-ups. as inputs, port 4 pins that are externally pulled low will source current because of the internal pull-ups. (note: when spen, i.e.,spctl.6, is 1, the pull-ups at these port pins are disabled.) 12 i ? p4.0, rxd1 C serial input port 1 (with pull-up on pin) i/o ? miso C spi master in/slave out (selected when sfr bit spen (spctl.6) is 1, in which case the pull-up for this pin is disabled) table 2: pin description continued symbol pin type description
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 9 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 34 o ? p4.1, txd1 C serial output port 1 (with pull-up on pin) i/o ? ss C spi slave select (selected when spen (spctl.6) is 1, in which case the pull-up for this pin is disabled) rst 10 i reset: a high on this pin for two machine cycles, while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v dd . ale 33 o address latch enable: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1 6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ale can be disabled by setting sfr auxr.0. with this bit is set, ale will be active only during a movx/emov/movc instruction. psen 32 o program store enable: the read strobe to external program memory. when executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea/v pp 35 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations. if ea is held high, the device executes from internal program memory. the value on the ea pin is latched when rst is released and any subsequent changes have no effect. xtal1 21 i crystal 1: input to the inverting oscillator ampli?er and input to the internal clock generator circuits. xtal2 20 o crystal 2: output from the inverting oscillator ampli?er. v ss 22 i ground: 0 v reference. v dd 44 i power supply: this is the power supply voltage for normal operation as well as idle and power down modes. (nc/v ss )1 i no connect/ground: this pin is internally connected to v ss on the p87c51mb2/mc2. if connected externally, this pin must only be connected to the same v ss as at pin 22. (note: connecting the second pair of v ss and v dd pins is not required. however, they may be connected in addition to the primary v ss and v dd pins to improve power distribution, reduce noise in output signals, and improve system-level emi characteristics.) (nc/v dd )23 i no connect/power supply: this pin is internally connected to v dd on the p87c51mb2/mc2. if connected externally, this pin must only be connected to the same v dd as at pin 44. (note: connecting the second pair of v ss and v dd pins is not required. however, they may be connected in addition to the primary v ss and v dd pins to improve power distribution, reduce noise in output signals, and improve system-level emi characteristics.) table 2: pin description continued symbol pin type description
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 10 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8. functional description 8.1 memory arrangement p87c51mb2 has 64 kbytes of otp (mx universal map range: 80:0000-80:ffff), while p87c51mc2 has 96 kbytes of otp (mx universal map range: 80:0000-81:7fff). the p87c51mb2 and p87c51mc2 have 2 kbytes and 3 kbytes of on-chip ram respectively: for more detailed information, please refer to the p87c51mx2 user manual or the 51mx architecture speci?cation . 8.2 special function registers special function register (sfr) accesses are restricted in the following ways: ? user must not attempt to access any sfr locations not de?ned. ? accesses to any de?ned sfr locations must be strictly for the functions for the sfrs. ? sfr bits labeled -, 0, or 1 can only be written and read as follows: C - must be written with 0, but can return any value when read (even if it was written with 0). it is a reserved bit and may be used in future derivatives. C 0 must be written with 0, and will return a 0 when read. C 1 must be written with 1, and will return a 1 when read. table 3: memory arrangement data memory size (bytes) and mx universal memory map range type description p87c51mb2 p87c51mc2 data memory that can be addressed both directly and indirectly; can be used as stack 128 (7f:0000-7f:007f) 128 (7f:0000-7f:001f) idata superset of data; memory that can be addressed indirectly (where direct address for upper half is for sfr only); can be used as stack 256 (7f:0000-7f:00ff) 256 (7f:0000-7f:00ff) edata superset of data/idata; memory that can be addressed indirectly using universal pointers (pr0,1); can be used as stack 512 (7f:0000-7f:01ff) 512 (7f:0000-7f:01ff) xdata memory (on-chip external data) that is accessed via the movx/emov instructions using dptr/eptr 1536 (00:0000-00:05ff) 2560 (00:0000-00:09ff)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. product data rev. 03 13 november 2003 11 of 36 table 4: special function registers name description sfr addr. bit functions and addresses reset value msb lsb bit address e7 e6 e5 e4 e3 e2 e1 e0 acc [1] accumulator e0h 00h auxr [2] auxiliary function register 8eh - - - - - - extram ao 00h [6] auxr1 [2] auxiliary function register 1 a2h - - - lpep gf2 0 - dps 00h [6] bit address f7 f6 f5 f4 f3 f2 f1 f0 b [1] b register f0h 00h brgcon [2] baud rate generator control 85h [3] - - - - - - s0brgs brgen 00h [6] brgr0 [2][5] baud rate generator rate low 86h [3] 00h brgr1 [2][5] baud rate generator rate high 87h [3] 00h ccap0h [2] module 0 capture high fah xxh ccap1h [2] module 1 capture high fbh xxh ccap2h [2] module 2 capture high fch xxh ccap3h [2] module 3 capture high fdh xxh ccap4h [2] module 4 capture high feh xxh ccap0l [2] module 0 capture low eah xxh ccap1l [2] module 1 capture low ebh xxh ccap2l [2] module 2 capture low ech xxh ccap3l [2] module 3 capture low edh xxh ccap4l [2] module 4 capture low eeh xxh ccapm0 [2] module 0 mode dah - ecom_0 capp_0 capn_0 mat_0 tog_0 pwm_0 eccf_0 00h [6] ccapm1 [2] module 1 mode dbh - ecom_1 capp_1 capn_1 mat_1 tog_1 pwm_1 eccf_1 00h [6] ccapm2 [2] module 2 mode dch - ecom_2 capp_2 capn_2 mat_2 tog_2 pwm_2 eccf_2 00h [6] ccapm3 [2] module 3 mode ddh - ecom_3 capp_3 capn_3 mat_3 tog_3 pwm_3 eccf_3 00h [6] ccapm4 [2] module 4 mode deh - ecom_4 capp_4 capn_4 mat_4 tog_4 pwm_4 eccf_4 00h [6] bit address df de dd dc db da d9 d8 ccon [1] [2] pca counter control d8h cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 00h [6] ch [2] pca counter high f9h 00h cl [2] pca counter low e9h 00h cmod [2] pca counter mode d9h cidl wdte - - - cps1 cps0 ecf 00h [6]
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. product data rev. 03 13 november 2003 12 of 36 dptr data pointer (2 bytes) 00h dph data pointer high 83h 00h dpl data pointer low 82h 00h eptr extended data pointer (3 bytes) epl [2] extended data pointer low fch [3] 00h epm [2] extended data pointer middle fdh [3] 00h eph [2] extended data pointer high feh [3] 00h bit address af ae ad ac ab aa a9 a8 ien0 [1] interrupt enable 0 a8h ea ec et2 es0/ es0r et1 ex1 et0 ex0 00h bit address ef ee ed ec eb ea e9 e8 ien1 [1] interrupt enable 1 e8h - - - - espi es1t es0t es1/ es1r 00h [6] bit address bf be bd bc bb ba b9 b8 ip0 [1] interrupt priority b8h - ppc pt2 ps0/ ps0r pt1 px1 pt0 px0 00h ip0h interrupt priority 0 high b7h - ppch pt2h ps0h/ ps0rh pt1h px1h pt0h px0h 00h bit address ff fe fd fc fb fa f9 f8 ip1 [1] interrupt priority 1 f8h - - - - pspi ps1t ps0t ps1/ ps1r 00h [6] ip1h interrupt priority 1 high f7h - - - - pspih ps1th ps0th ps1h/ ps1rh 00h [6] mxcon [2] mx control register ffh [3] - - - ecrm eam1 eam0 esmm eifm 00h [6] bit address 87 86 85 84 83 82 81 80 p0 [1] port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1 [1] port 1 90h cex4 cex3 cex2/ spiclk cex1/ mosi cex0 eci t2ex t2 ffh table 4: special function registers continued name description sfr addr. bit functions and addresses reset value msb lsb
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. product data rev. 03 13 november 2003 13 of 36 bit address a7 a6 a5 a4 a3 a2 a1 a0 p2 [1] port 2 a0h ad15 ad14/ ad22 ada13/ ad21 ad12/ ad20 ad11/ ad19 ad10/ ad18 ad9/ ad17 ad8/ ad16 ffh bit address b7 b6 b5 b4 b3 b2 b1 b0 p3 [1] port 3 b0h rd wr t1 t0 int1 int0 txd0 rxd0 ffh bit address c7 [3] c6 [3] c5 [3] c4 [3] c3 [3] c2 [3] c1 [3] c0 [3] p4 [1] [2] port 4 c0h [3] - - - - - - txd1/ ss rxd1/ miso ffh pcon [2] power control register 87h smod1 smod0 - pof gf1 gf0 pd idl 00h/ 10h [4] pcona [2] power control register a b5h - pcapd - spipd brgpd t2pd s1pd s0pd bit address d7 d6 d5 d4 d3 d2 d1 d0 psw [1] program status word d0h cy ac f0 rs1 rs0 ov f1 p 00h rcap2h [2] timer2 capture high cbh 00h rcap2l [2] timer2 capture low cah 00h bit address 9f 9e 9d 9c 9b 9a 99 98 s0con [1] serial port 0 control 98h sm0_0/ fe_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 00h s0buf serial port 0 data buffer register 99h xxh s0addr serial port 0 address register a9h 00h s0aden serial port 0 address enable b9h 00h s0stat [2] serial port 0 status 8ch [3] dbmod_0 intlo_0 cidis_0 dbisel_ 0 fe_0 br_0 oe_0 stint_0 00h [6] bit address 87 [3] 86 [3] 85 [3] 84 [3] 83 [3] 82 [3] 81 [3] 80 [3] s1con [1] [2] serial port 1 control 80h [3] sm0_1/ fe_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 00h s1buf [2] serial port 1 data buffer register 81h [3] xxh s1addr [2] serial port 1 address register 82h [3] 00h s1aden [2] serial port 1 address enable 83h [3] 00h table 4: special function registers continued name description sfr addr. bit functions and addresses reset value msb lsb
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. product data rev. 03 13 november 2003 14 of 36 [1] sfrs are bit addressable. [2] sfrs are modi?ed from or added to the 80c51 sfrs. [3] extended sfrs accessed by preceding the instruction with mx escape (opcode a5h). [4] power on reset is 10h. other reset is 00h. [5] brgr1 and brgr0 must only be written if brgen in brgcon sfr is 0. if any of them is written if brgen = 1, result is unpredic table. [6] the unimplemented bits (labeled -) in the sfrs are xs (unknown) at all times. 1s should not be written to these bits, as they may be used for other purposes in future derivatives. the reset values shown for these bits are 0s although they are unknown when read. s1stat [2] serial port 1 status 84h [3] dbmod_1 intlo_1 cidis_1 dbisel1 fe_1 br_1 oe_1 stint_1 00h [6] spctl [2] spi control register e2h ssig spen dord mstr cpol cpha psc1 psc0 00h [6] spcfg [2] spi con?guration register e1h spif spwcol - - - - - - 00h [6] spdat [2] spi data e3h 00h sp stack pointer (or stack pointer low byte when edata supported) 81h 07h spe [2] stack pointer high fbh [3] 00h bit address 8f 8e 8d 8c 8b 8a 89 88 tcon [1] timer control register 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con [1] [2] timer2 control register c8h tf2 exf2 rclk tclk exen2 tr2 c/ t 2 cp/ rl2 00h t2mod [2] timer2 mode control c9h - - ent2 tf2de t2gate t2pwme t2oe dcen 00h [6] th0 timer 0 high 8ch 00h th1 timer 1 high 8dh 00h th2 timer 2 high cdh 00h tl0 timer 0 low 8ah 00h tl1 timer 1 low 8bh 00h tl2 timer 2 low cch 00h tmod timer 0 and 1 mode 89h gate c/t m1 m0 gate c/t m1 m0 00h wdtrst [2] watchdog timer reset a6h ffh wdcon [2] watchdog timer control 8fh [3] - - - - - wdpre2 wdpre1 wdpre0 00h [6] table 4: special function registers continued name description sfr addr. bit functions and addresses reset value msb lsb
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 15 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 8.3 security bits the p87c51mx2 has security bits to protect users ?rmware codes. with none of the security bits programmed, the code in the program memory can be veri?ed. when only security bit 1 (see ta b l e 5 ) is programmed, movc instructions executed from external program memory are disabled from fetching code bytes from the internal memory. ea is latched on reset and all further programming of eprom is disabled. when security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. when all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. [1] p - programmed. u - unprogrammed. [2] any other combination of security bits is not de?ned. 9. limiting values [1] the following applies to the limiting values: a) stresses above those listed under limiting values may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in section 10 static characteristics and section 11 dynamic characteristics of this speci?cation is not implied. b) this product includes circuitry speci?cally designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated max ima. c) parameters are valid over operating temperature range unless otherwise speci?ed. all voltages are with respect to v ss unless otherwise noted. table 5: eprom security bits security bits [1][2] bit 1 bit 2 bit 3 protection description 1 u u u no program security features enabled. eeprom is programmable and veri?able. 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 p p u same as 2, also veri?cation is disabled. 4 p p p same as 3, external execution is disabled. table 6: limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit t amb operating temperature under bias 0 +70 c t stg storage temperature range - 65 +150 c v i input voltage on ea/v pp pin to v ss 0 +13 v input voltage on any other pin to v ss - 0.5 v dd + 0.5 v v i i , i o maximum i ol per i/o pin - 20 ma p power dissipation based on package heat transfer, not device power consumption - 1.5 w
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 16 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 10. static characteristics [1] typical ratings are not guaranteed. the values listed are at room temperature (+25 ?c), 5 v, unless otherwise stated. [2] capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol of ale and ports 1, 3 and 4. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading >100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5 ma and no more than two outputs exceed the test conditions. [3] capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v dd - 0.7 v speci?cation when the address bits are stabilizing. [4] pins of ports 1, 2, 3 and 4 source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in is approximately 2 v for 4.5 v < v dd < 5.5 v. [5] see figure 13 through figure 16 for i cc test conditions. f osc is the oscillator frequency in mhz. table 7: static characteristics t amb =0 cto + 70 c for commercial, unless otherwise speci?ed; v dd = 2.7 v to 5.5 v unless otherwise speci?ed. symbol parameter conditions min typ [1] max unit v il input low voltage - 0.5 0.2v dd - 0.1 v v ih input high voltage (ports 0, 1, 2, 3, 4, ea) 0.2v dd +0.9 v dd +0.5 v v ih1 input high voltage, xtal1, rst 0.7v dd v dd +0.5 v v ol output low voltage, ports 1, 2, 3, 4 [8] v dd = 4.5 v, i ol = 1.6 ma - 0.4 v v dd = 2.7 v, i ol = 1.6 ma v ol1 output low voltage, port 0, ale, psen [7][8] v dd = 4.5 v, i ol = 3.2 ma - 0.4 v v dd = 2.7 v, i ol = 3.2 ma v oh output high voltage, ports 1, 2, 3, 4 v dd = 4.5 v, i oh = - 30 a v dd - 0.7 - v v dd = 2.7 v, i oh = - 10 a - v oh1 output high voltage (port 0 in external bus mode), ale [9] , psen [3] v dd = 4.5 v, i oh = - 3.2 ma v dd - 0.7 - v v dd = 2.7 v, i oh = - 3.2 ma i il logical 0 input current, ports 1, 2, 3, 4 v in = 0.4 v - 1 - 75 m a i tl logical 1-to-0 transition current, ports 1, 2, 3, 4 [8] 4.5 v < v dd < 5.5 v, v in = 2.0 v [4] - - 650 m a i l1 input leakage current, port 0 0.45 < v in < v dd - 0.3 - 10 m a i cc power supply current [5] - active mode [5] v dd = 5.5 v - 7 + 2.7 /mhz f osc ma v dd = 3.6 v - 4 + 1.3 /mhz f osc idle mode [5] v dd = 5.5 v - 4 + 1.3 /mhz f osc ma v dd = 3.6 v - 1 + 1.0 /mhz f osc power-down mode or clock stopped (see figure 16 for conditions) v dd = 5.0 v - 20 - m a v dd = 5.5 v - 100 m a r rst internal reset pull-down resistor 40 225 k w c 10 pin capacitance [10] (except ea) -15pf
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 17 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. [6] this value applies to t amb =0 c to +70 c. [7] load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. [8] under steady state (non-transient) conditions, i ol must be externally limited as follows: a) maximum i ol per port pin: 15 ma b) maximum i ol per 8-bit port: 26 ma c) maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related speci?cation. pins are not guaranteed to sink current greater than the listed test conditions. [9] ale is tested to v oh1 , except when ale is off then v oh is the voltage speci?cation. [10] pin capacitance is characterized but not tested.
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 18 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 11. dynamic characteristics table 8: dynamic characteristics t amb = 0 to +70 c for commercial unless otherwise speci?ed. formulae including t clcl assume oscillator signal with 50/50 duty cycle. [1][2][3] symbol fig parameter 2.7 v < v dd < 5.5 v 4.5 v < v dd < 5.5 v unit variable clock [4] f osc = 12 mhz [4] variable clock [4] f osc = 24 mhz [4] min max min max min max min max f osc 4 oscillator frequency 0 12 - 0 24 - mhz t clcl 4 clock cycle - - 83 - - 41.5 - ns t lhll 4 ale pulse width t clcl - 15 - 68 - t clcl - 15 - 26 - ns t avll 4 , 5 , 6 address valid to ale low 0.5t clcl - 15 - 8 - 0.5t clcl - 15 - 5 - ns t llax 4 , 5 , 6 address hold after ale low 0.5t clcl - 25 - 16 - 0.5t clcl - 15 - 5 - ns t lliv 4 ale low to valid instruction in - 0.5t clcl - 25 121 - 2t clcl - 30 53 ns t llpl 4 ale low to psen low 0.5t clcl - 25 - 16 - 0.5t clcl - 12 - 8 - ns t plph 4 psen pulse width 1.5t clcl - 25 - 100 - 1.5t clcl - 20 - 42 - ns t pliv 4 psen low to valid instruction in - 1.5t clcl - 45 - 80 - 1.5t clcl - 35 27 ns t pxix 4 input instruction hold after psen 0- 0-0-0-ns t pxiz 4 input instruction ?oat after psen - 0.5t clcl - 10 - 31 - 0.5t clcl - 5 - 15 ns t aviv 4 address to valid instruction in (non-extended addressing mode) - 2.5t clcl - 35 - 173 - 2.5t clcl - 30 - 74 ns t aviv1 4 address (a16-a22) to valid instruction in (extended addressing mode) - 1.5t clcl - 44 - 81 - 1.5t clcl - 34 - 28 ns t plaz 4 psen low to address ?oat - 16 - 16 - 8 - 8 ns
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 19 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. data memory t rlrh 5 rd pulse width 3t clcl - 25 - 225 - 3t clcl - 20 - 105 - ns t wlwh 6 wr pulse width 3t clcl - 25 - 225 - 3t clcl - 20 - 105 - ns t rldv 5 rd low to valid data in - 2.5t clcl - 55 - 153 - 2.5t clcl - 40 - 64 ns t rhdx 5 data hold after rd 0- 0-0-0-ns t rhdz 5 data ?oat after rd -t clcl - 20 - 63 - t clcl - 15 - 26 ns t lldv 5 ale low to valid data in -4t clcl - 50 - 283 - 4t clcl - 35 - 131 ns t avdv 5 address to valid data in (non-extended addressing mode) - 4.5t clcl - 40 - 335 - 4.5t clcl - 30 - 157 ns t avdv1 5 address (a16-a22) to valid data in (extended addressing mode) - 3.5t clcl - 45 - 246 - 3.5t clcl - 35 - 110 ns t llwl 5 , 6 ale low to rd or wr low 1.5t clcl - 5 1.5t clcl +20 120 145 1.5t clcl - 10 1.5t clcl +20 52 82 ns t avwl 5 , 6 address valid to wr or rd low (non-extended addressing mode) 2t clcl - 5 - 161 - 2t clcl - 5 - 78 - ns t avwl1 5 , 6 address (a16-a22) valid to wr or rd low (extended addressing mode) t clcl - 10 - 73 - t clcl - 10 - 31 - ns t qvwx 6 data valid to wr transition 0.5t clcl - 20 - 21 - 0.5t clcl - 15 - 5 - ns t whqx 6 data hold after wr 0.5t clcl - 25 - 16 - 0.5t clcl - 11 - 9 - ns t qvwh 6 data valid to wr high 3.5t clcl - 10 - 281 - 3.5t clcl - 10 - 135 - ns table 8: dynamic characteristics continued t amb = 0 to +70 c for commercial unless otherwise speci?ed. formulae including t clcl assume oscillator signal with 50/50 duty cycle. [1][2][3] symbol fig parameter 2.7 v < v dd < 5.5 v 4.5 v < v dd < 5.5 v unit variable clock [4] f osc = 12 mhz [4] variable clock [4] f osc = 24 mhz [4] min max min max min max min max
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 20 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. t rlaz 5 rd low to address ?oat -0-0-0-0ns t whlh 5 , 6 rd or wr high to ale high 0.5t clcl - 20 0.5t clcl +10 21 51 0.5t clcl - 11 0.5t clcl +10 9 30 ns external clock t chcx 12 high time 33 t clcl - t clcx 33 - 16 t clcl - t clcx 16 - ns t clcx 12 low time 33 t clcl - t chcx 33 - 16 t clcl - t chcx 16 - ns t clch 12 rise time - 8 - 8 - 4 - 4 ns t chcl 12 fall time - 8 - 8 - 4 - 4 ns shift register t xlxl 7 serial port clock cycle time 6t clcl - 500 - t clcl - t clcx - 250 - ns t qvxh 7 output data setup to clock rising edge 5t clcl - 10 - 406 - t clcl - t chcx - 198 - ns t xhqx 7 output data hold after clock rising edge t clcl - 10 - 68 - t clcl - 15 - 26 - ns t xhdx 7 input data hold after clock rising edge 0- 0-0-0-ns t xhdv 7 clock rising edge to input data valid -5t clcl - 55 - 361 - 5t clcl - 35 - 173 ns spi interface f spi mhz -------- 0 2.0 0 2.0 0 2.0 0 2.0 -------- 0 3.0 0 3.0 0 3.0 0 3.0 t spicyc 8 , 9 , 10 , 11 cycle time ns 2.0 mhz (master) -------- 2.0 mhz (slave) 500 - 500 - 500 - 500 - 3.0 mhz (master) -------- 3.0 mhz (slave) 333 - 333 - 333 - 333 - table 8: dynamic characteristics continued t amb = 0 to +70 c for commercial unless otherwise speci?ed. formulae including t clcl assume oscillator signal with 50/50 duty cycle. [1][2][3] symbol fig parameter 2.7 v < v dd < 5.5 v 4.5 v < v dd < 5.5 v unit variable clock [4] f osc = 12 mhz [4] variable clock [4] f osc = 24 mhz [4] min max min max min max min max
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 21 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. t spilead 10 , 11 enable lead time (slave) ns 2.0 mhz 250 - 250 - 250 - 250 - 3.0 mhz 240 - 240 - 240 - 240 - t spilag 10 , 11 enable lag time (slave) ns 2.0 mhz 250 - 250 - 250 - 250 - 3.0 mhz 240 - 240 - 240 - 240 - t spiclkh 8 , 9 , 10 , 11 spiclk high time ns master 340 - 340 - 340 - 340 - slave 190 - 190 - 190 - 190 - t spiclkl 8 , 9 , 10 , 11 spiclk low time ns master 340 - 340 - 340 - 340 - slave 190 - 190 - 190 - 190 - t spidsu 8 , 9 , 10 , 11 data setup time (master or slave) 100 - 100 - 100 - 100 - ns t spidh 8 , 9 , 10 , 11 data hold time (master or slave) 100 - 100 - 100 - 100 - ns t spia 10 , 11 access time (slave) 0 120 0 120 0 120 0 120 ns t spidis 10 , 11 disable time (slave) ns 2.0 mhz 0 240 - 240 0 240 - 240 3.0 mhz 0 167 - 167 0 167 - 167 t spidv 8 , 9 , 10 , 11 enable to output data valid ns 2.0 mhz - 240 - 240 - 240 - 240 3.0 mhz - 167 - 167 - 167 - 167 t spioh 8 , 9 , 10 , 11 output data hold time 0- 0-0-0-ns table 8: dynamic characteristics continued t amb = 0 to +70 c for commercial unless otherwise speci?ed. formulae including t clcl assume oscillator signal with 50/50 duty cycle. [1][2][3] symbol fig parameter 2.7 v < v dd < 5.5 v 4.5 v < v dd < 5.5 v unit variable clock [4] f osc = 12 mhz [4] variable clock [4] f osc = 24 mhz [4] min max min max min max min max
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 22 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. [1] parameters are valid over operating temperature range unless otherwise speci?ed. [2] load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. [3] interfacing the microcontroller to devices with ?oat times up to 45 ns is permitted. this limited bus contention will not cau se damage to port 0 drivers. [4] parts are tested down to 2 mhz, but are guaranteed to operate down to 0 hz. t spir 8 , 9 , 10 , 11 rise time ns spi outputs (spiclk, mosi, miso) - 100 - 100 - 100 - 100 spi outputs (spiclk, mosi, miso, ss) - 2000 - 2000 - 2000 - 2000 t spif 8 , 9 , 10 , 11 fall time ns spi outputs (spiclk, mosi, miso) - 100 - 100 - 100 - 100 spi outputs (spiclk, mosi, miso, ss) - 2000 - 2000 - 2000 - 2000 table 8: dynamic characteristics continued t amb = 0 to +70 c for commercial unless otherwise speci?ed. formulae including t clcl assume oscillator signal with 50/50 duty cycle. [1][2][3] symbol fig parameter 2.7 v < v dd < 5.5 v 4.5 v < v dd < 5.5 v unit variable clock [4] f osc = 12 mhz [4] variable clock [4] f osc = 24 mhz [4] min max min max min max min max
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 23 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 11.1 explanation of ac symbols each timing symbol has ?ve characters. the ?rst character is always t (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll time for address valid to ale low t llpl time for ale low to psen low
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 24 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. fig 4. external program memory read cycle (extended memory cycle). t plph t pxiz t lliv t aviv1 t aviv p2.0-p2.7 or a8-a15 instr in a0-a7 t avll t llax t pxix t llpl t pliv t plaz t lhll a0-a7 p2.0-p2.7 or a8-a15 or a16-a22,p2.7 ale port 0 port 2 psen 002aaa150 fig 5. external data memory read cycle. t rhdz t avdv1 t avwl1 t avwl t llwl t whlh t rlaz t rldv data i n a0-a7 from pcl instr in t avll t llax t rhdx t lldv t rlrh a0-a7 ale port 0 port 2 psen rd 002aaa151 p2.0-p2.7 or a8-a15 p2.0-p2.7 or a8-a15 or a16-a22,p2.7 t avdv
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 25 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. fig 6. external data memory write cycle. t whqx t avwl t avwl1 t llwl t whlh t qvwx data out a0-a7 from pcl instr in t avll t llax t qvwh t wlwh a0-a7 ale port 0 port 2 psen wr 002aaa153 p2.0-p2.7 or a8-a15 p2.0-p2.7 or a8-a15 or a16-a22,p2.7 fig 7. shift register mode timing. t xlxl instruction ale clock output data write to sbuf input data t qvxh t xhqx t xhdv t xhdx 012345678 1 0 234567 valid valid valid valid valid valid valid valid clear ri set ti set ri 002aaa155
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 26 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. fig 8. spi master timing (cpha = 0). t clcl t spiclkh t spiclkl master lsb/msb out master msb/lsb out t spidh t spidsu t spiclkl t spiclkh t spif t spioh t spidv t spir t spidv t spif t spif t spir t spir ss spiclk (cpol = 0) (output) 002aaa156 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in fig 9. spi master timing (cpha = 1). t clcl t spiclkl t spiclkh master lsb/msb out master msb/lsb out t spidh t spidsu t spiclkh t spiclkl t spif t spioh t spidv t spidv t spir t spidv t spif t spir t spif t spir ss spiclk (cpol = 0) (output) 002aaa157 spiclk (cpol = 1) (output) miso (input) mosi (output) lsb/msb in msb/lsb in
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 27 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. fig 10. spi slave timing (cpha = 0). t clcl t spiclkh t spiclkl t spilead t spiclkh t spiclkl t spilag t spidsu t spidh t spidh t spidsu t spidsu t spir t spia t spioh t spioh t spidis t spir slave msb/lsb out msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spidv t spir t spif t spir t spif ss spiclk (cpol = 0) (input) 002aaa158 spiclk (cpol = 1) (input) miso (output) mosi (input) not defined fig 11. spi slave timing (cpha = 1). t clcl t spiclkh t spiclkl t spilead t spiclkh t spiclkl t spilag t spidsu t spidh t spidh t spidsu t spir t spia t spioh t spidis t spir slave msb/lsb out not defined msb/lsb in lsb/msb in slave lsb/msb out t spidv t spioh t spidv t spioh t spidv t spir t spif t spir t spif ss spiclk (cpol = 0) (input) 002aaa159 spiclk (cpol = 1) (input) miso (output) mosi (input) t spidsu
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 28 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. fig 12. external clock drive. t chcl t clcx t chcx t clcl t clch 002aaa160 0.7 v dd 0.2 v dd -0.1 v v dd -0.5 v 0.45 v fig 13. i cc test condition, active mode (all other pins are disconnected). xtal2 rst v dd p0 ea xtal1 v ss 002aaa161 i cc v dd v dd v dd clock signal (nc) fig 14. i cc test condition, idle mode (all other pins are disconnected). xtal2 rst v dd p0 ea xtal1 v ss 002aaa162 i cc v dd v dd clock signal (nc)
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 29 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. fig 15. clock signal waveform for i cc tests in active and idle modes (t clch =t chcl = 5 ns). t chcl t clcx t chcx t clcl t clch 002aaa163 0.7 v dd 0.2 v dd -0.1 v v dd -0.5 v 0.45 v fig 16. i cc test condition, power-down mode (all other pins are disconnected, v dd = 2.0 v to 5.5 v). xtal2 rst v dd p0 ea xtal1 v ss i cc v dd v dd (nc) 002aaa164
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 30 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 12. package outline fig 17. sot187-2. unit a a 1 min. a 4 max. b p ey w v b references outline version european projection issue date iec jedec jeita mm 4.57 4.19 0.51 3.05 0.53 0.33 0.021 0.013 16.66 16.51 1.27 17.65 17.40 2.16 45 o 0.18 0.1 0.18 dimensions (mm dimensions are derived from the original inch dimensions) note 1. plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. sot187-2 d (1) e (1) 16.66 16.51 h d h e 17.65 17.40 z d (1) max. z e (1) max. 2.16 b 1 0.81 0.66 k 1.22 1.07 0.180 0.165 0.02 0.12 a 3 0.25 0.01 0.656 0.650 0.05 0.695 0.685 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.656 0.650 0.695 0.685 e d e e 16.00 14.99 0.63 0.59 16.00 14.99 0.63 0.59 0.085 0.032 0.026 0.048 0.042 29 39 44 1 6 717 28 18 40 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k x y e e b d h e e e h v m b d z d a z e e v m a pin 1 index 112e10 ms-018 edr-7319 0 5 10 mm scale 99-12-27 01-11-14 inches plcc44: plastic leaded chip carrier; 44 leads sot187-2 d e
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 31 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 13. soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 13.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 32 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 13.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 9: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 33 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages.
philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family product data rev. 03 13 november 2003 34 of 36 9397 750 12302 ? koninklijke philips electronics n.v. 2003. all rights reserved. 14. revision history table 10: revision history rev date cpcn description 03 20031113 - product data (9397 750 12302); ecn 853-2426 01-a14402 dated 6 november 2003 modi?cations: ? figure 5 external data memory read cycle. on page 24 ; added t rldv , removed non-extended memory cycle from ?gure title. ? figure 6 external data memory write cycle. on page 25 ; removed non-extended memory cycle from ?gure title. 02 20030519 - product data (9397 750 11517) _1 20010406 - preliminary speci?cation (9397 750 08199)
9397 750 12302 philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family ? koninklijke philips electronics n.v. 2003. all rights reserved. product data rev. 03 13 november 2003 35 of 36 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2003. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 13 november 2003 document order number: 9397 750 12302 contents philips semiconductors p87c51mb2/p87c51mc2 80c51 8-bit microcontroller family 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 key bene?ts . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.3 complete features . . . . . . . . . . . . . . . . . . . . . . 2 3 differences between p87c51mx2/02 part and previous revisions of p87c51mx2 . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 functional description . . . . . . . . . . . . . . . . . . 10 8.1 memory arrangement . . . . . . . . . . . . . . . . . . . 10 8.2 special function registers . . . . . . . . . . . . . . . 10 8.3 security bits . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 15 10 static characteristics. . . . . . . . . . . . . . . . . . . . 16 11 dynamic characteristics . . . . . . . . . . . . . . . . . 18 11.1 explanation of ac symbols. . . . . . . . . . . . . . . 23 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 30 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 31 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31 13.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 32 13.5 package related soldering information . . . . . . 32 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 34 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 35 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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